Essenceia/CRC_generator

CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible. Written by Evgeni Stavinov.

13 best points · 3 comments · 1 Hacker News post · 4 GitHub stars · View on GitHub

Hacker News discussions

• Trying to preserve other peoples code (13 points, 3 comments, by random__duck, 2026-05-23)