SpinalHDL/VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

121 best points · 97 comments · 2 Hacker News posts · 3,303 GitHub stars · View on GitHub

Hacker News discussions

• A FPGA friendly 32 bit RISC-V CPU implementation (121 points, 54 comments, by _benj, 2025-01-22)
• An FPGA-friendly 32-bit RISC-V CPU implementation (102 points, 43 comments, by Dolu, 2017-07-19)