bluespec/Flute

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

6 best points · 0 comments · 2 Hacker News posts · 384 GitHub stars · View on GitHub

Hacker News discussions

• Flute: RISC-V CPU, simple 5-stage in-order pipeline (6 points, 0 comments, by EvgeniyZh, 2018-12-27)
• RISC-V CPU with simple 5-stage in-order pipeline for FPGA (2 points, 0 comments, by EvgeniyZh, 2018-10-03)