stnolting/neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

2 best points · 0 comments · 1 Hacker News post · 101 GitHub stars · View on GitHub

Hacker News discussions

• Show HN: Convert VHDL to Verilog using GHDL (+ first evaluation) (2 points, 0 comments, by youre_the_voice, 2022-08-28)